Researcher(s)
- Salman Chowdhury, Electrical Engineering, University of Delaware
Faculty Mentor(s)
- Ujjwal Das, Institute of Enerdy Conversion, University of Delaware
Abstract
Diode parameters are the most sensitive indicators of degradation in photovoltaic devices, since these parameters directly limit fill factor and maximum power output. Thermal stress can alter contact quality, recombination defects, and carrier transport, but the rate at which these losses develop during annealing is not well characterized at the individual cell level. Carrying out the analysis for each cell is slow and varies between operators, since each parameter requires numerically differentiating the measured curves and fitting a separate region of the result, which limits how many temperatures can practically be compared. The established procedure was therefore implemented as a Python program that reads raw J-V files directly, automatically selects the fitting regions for each parameter, and outputs diagnostic plots and a tabulated parameter summary for every cell in a batch.The purpose of this study was to evaluate how annealing at different temperatures affects the resistive behavior and diode parameters of silicon heterojunction solar cells.
Baseline current density-voltage (J-V) measurements were taken under one-sun illumination, with paired dark J-V scans over the same voltage range. Diode parameters were extracted from these curves: series resistance from the slope of dV/dJ against inverse current density, shunt conductance from the slope near short circuit, and ideality factor and saturation current density from a semilog fit of the resistance-corrected characteristic. Cells were then annealed at a series of temperatures, with the full light and dark J-V sequence repeated after each treatment so that open-circuit voltage, short-circuit current density, fill factor, maximum power output, and series resistance could be tracked across conditions. A representative baseline cell showed an efficiency of 16.95%, with a dark and light ideality factor approximately at 1.81 Annealing is expected to raise series resistance and ideality factor while lowering fill factor, consistent with degradation of the diode and of minority carrier transport.
Future work will extend the annealing range and correlate the observed parametric changes to identify the mechanism behind the loss.