RTL-to-Layout Design and Power Side-Channel Vulnerability Evaluation

• Ryan Henderson, Electrical Engineering, University of Delaware

• Chengmo Yang, ECE, University of Delaware
• Saeid Rajabi, ECE, University of Delaware

Cryptographic hardware such as Advanced Encryption Standard (AES) implementations must be evaluated for physical security vulnerabilities, including power-based side-channel leakage. Traditionally, these evaluations have relied on proprietary chip design tools that impose high costs and restrict flexibility. This project addressed that challenge by constructing a complete RTL-to-layout design flow using only open-source electronic design automation (EDA) tools. The design process began with a Verilog description of an AES encryption core, which was synthesized using Yosys and then placed and routed using the OpenROAD Flow Scripts framework. The resulting layout and gate-level netlist enabled post-layout simulation to estimate dynamic power consumption. Switching activity was captured and converted into time-based power traces, representing the chip’s behavior across clock cycles or toggles. These power traces allowed for a general evaluation of the circuit’s vulnerability to power side-channel leakage. The use of open-source tools provided a cost-effective, customizable, and collaborative environment, removing the need for commercial licenses while still achieving practical and reproducible results. The project demonstrated that open-source flows are capable of supporting meaningful hardware security research and early-stage power analysis without proprietary software dependencies.